The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
The continuing decrease in technology nodes has lead to a desire to replace a conventional polysilicon gate electrode with a metal gate electrode to improve device performance. One process for forming a metal gate structure (i.e., having a metal gate electrode) is referred to as a “gate last” process, where a final gate stack is fabricated last. This reduces the number of subsequent processes, including high temperature processing, that must be performed after formation of the gate structure. However, there are challenges to implementing such features and processes in conventional fabrication. As the gate length and spacing between devices decreases, these problems are exacerbated. For example, conventional gate replacement processes have limited thermal budgets, which limits flexibility in metal gate work function tuning. The limited thermal budgets can arise because contact features (e.g., silicide regions of source/drain regions) are formed prior to the gate replacement process. The contact features have low thermal budgets. Consequently, if the gate replacement processes employ temperatures exceeding the contact features' thermal budget, such as a high temperature annealing process, the contact features are damaged. Accordingly, what is needed is an improved method for fabricating an IC device.